FIG. 1 is a block diagram of a wireless communication system.
The wireless communication system has a transmission unit and a reception unit. The transmission unit has an oscillator 11 configured to generate a high-frequency signal used as a carrier signal, a transmission side baseband circuit 13, a modulation circuit 12 configured to modulate a baseband signal with a high-frequency signal, a high-output amplifier 14 configured to amplify a modulated signal, and a transmission antenna 15. The reception unit has a reception antenna 21, a low noise amplifier (LNA) 22 configured to amplify a received signal, a demodulation circuit 23 configured to demodulate an amplified received signal, and a reception side baseband circuit 24 configured to process a demodulated baseband signal. The configuration of the wireless communication system illustrated in FIG. 1 is widely known, and therefore detailed explanation is omitted.
As illustrated in FIG. 1, a received signal received by the reception antenna 21 in the reception unit is amplified by the low noise amplifier 22. Although the below explained amplifier relates to a low noise amplifier configured to amplify a high-frequency signal used in the wireless communication system such as in FIG. 1, the amplifier is not limited to the low noise amplifier.
The performance of a low noise amplifier is evaluated by the amplification gain, the noise characteristics, the frequency characteristics, and the dynamic range (magnitude of the power level that can be handled).
In the communication system such as in FIG. 1, when a transmitter is arranged in close proximity to a receiver, and when the transmitted power is reflected at a very short distance, etc., the situation of an excessive input may occurs in which electric power larger than the supposed electric power is input. In general, the low noise amplifier is formed by a field effect transistor (FET), such as a MES (Metal-Semiconductor) FET and a HEMT whose size is small, and therefore the low noise amplifier is easily destroyed by large electric power. Thus, if an excessive input occurs, the FET included in the low noise amplifier may be destroyed.
FIG. 2 is a diagram explaining a mechanism of destruction of a field effect transistor (FET) when large electric power is input to an amplifier formed by a FET whose source is grounded. In FIG. 2, for simplification of explanation, a sinusoidal wave is input to an amplifier.
As illustrated in FIG. 2, the amplifier has a FET 34, an input side matching circuit 32 connected between an input port 31 and the gate terminal of the FET 34, a voltage source 33, and an output side matching circuit 35 connected between an output port 36 and the drain terminal of the FET 34. The source of the FET 34 is connected to a ground GND (grounded). The input side matching circuit 32 has impedance elements 41, 42, and 43 connected as illustrated in FIG. 2, and performs the impedance matching between the input port 31 and the gate terminal of the FET 34. The impedance element 42 is connected to the ground (GND) via the voltage source 33 that outputs a gate bias voltage. Thus, the voltage at the node of the input side matching circuit 32 changes in accordance with the voltage of a high-frequency input signal with the gate bias voltage as a center value and is applied to the gate of the FET 34. The gate bias voltage is set so that the gain of amplification by the FET 34 becomes high and, for example, when a depression-type FET is used, the voltage is about −2 to 0 V. In the following explanation, e the input side matching circuit 32 and the voltage source 33 may be together referred to as an input side matching circuit.
The output side matching circuit 35 performs the impedance matching between the drain terminal of the FET 34 and the output port 36. Although not illustrated, the output side matching circuit 35 is provided with a voltage source that supplies a direct-current voltage in accordance with the necessity and the output side matching circuit 35 with the voltage source included may be referred to as an output side matching circuit.
The circuit configuration of the amplifier in FIG. 2 is a widely known circuit configuration in which the source of the FET 34 is grounded.
In the amplifier in FIG. 2, although when the input signal is small, no problem occurs, when the input signal becomes large and the voltage becomes positive as illustrated at A point, if the voltage level becomes higher than the on-voltage of a diode that is formed between the gate and the source of the FET 34, a current flows between the gate and the source. The current becomes large as the voltage value becomes large, and when the current exceeds a certain level, the gate of the FET 34 is destroyed. In particular, a high-frequency FET is formed by a fine gate, and therefore the high-frequency FET may be easily destroyed.
Although the destruction withstand voltage may be increased by using a large-size FET or a FET having a high withstand voltage, the withstand voltage is increased by devising a circuit.
Related Documents
[Patent Document 1] WO 2007/99622
[Patent Document 2] Japanese Laid Open Patent Document No. H3-158008
[Patent Document 3] Japanese Laid Open Patent Document No. 2014-175675